ATMEGA649V-8MI【PDF 128/146 页】IC AVR MCU FLASH 64K 1.8V 64QFN

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2552K–AVR–04/11

ATmega329/3290/649/6490

Bit 5 – PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an inter-

rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT1

Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.

Bit 4 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.

The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT0 Inter-

rupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.

Bit 0 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the

External Interrupt Control Register A (EICRA) define whether the external interrupt is activated

on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an

interrupt request even if INT0 is configured as an output. The corresponding interrupt of External

Interrupt Request 0 is executed from the INT0 Interrupt Vector.

12.2.3

EIFR – External Interrupt Flag Register

Bit 7 – PCIF3: Pin Change Interrupt Flag 3

When a logic change on any PCINT30..24 pin triggers an interrupt request, PCIF3 becomes set

(one). If the I-bit in SREG and the PCIE3 bit in EIMSK are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

This bit is reserved bit in ATmega329/649 and will always be read as zero.

Bit 6 – PCIF2: Pin Change Interrupt Flag 2

When a logic change on any PCINT24..16 pin triggers an interrupt request, PCIF2 becomes set

(one). If the I-bit in SREG and the PCIE2 bit in EIMSK are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

This bit is reserved bit in ATmega329/649 and will always be read as zero.

Bit 5 – PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set

(one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

Bit

654

0x1C (0x3C)

PCIF3

PCIF2

PCIF1

PCIF0

–

INTF0

EIFR

Read/Write

R/W

Initial Value

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